In general, to achieve faster operation in a microprocessor, the instructions are broken in tasks. Then, the tasks are processed in parallel. This implementation technique is known as “pipelining”. This technique is widely used for fast processing in modem microprocessors. Typically, an instruction may be divided into 5 stages: 1) fetch the instruction; 2) decode the instruction; 3) fetch the operands if necessary; 4) execute the instruction; and 5) store the results if necessary. A stage may be separated into parts depending on the application. FIG. 1 shows an example of instruction execution with/without pipelining. The top part in the FIG. 1 shows processes without the pipelining. In this case, instructions are executed sequentially. Thus, instruction 1 (2) is followed by the instruction 2 (4) after the instruction 1 (2) is complete. After the instruction 2 (4) is complete, the instruction 3 (6) starts. However, in processes with the pipelining as shown in the bottom part in the FIG. 1, when the instruction passes to the next step in the stage, a new instruction starts. Thus, instruction 1, (8) instruction 2 (10), and instruction 3 (12) are executed in parallel. The execution time is shorter than in the execution without the pipelining. As a result, this parallel execution achieves faster data processing.
In design of a microprocessor, a major concern is not only the faster operations but also power requirements. The power distribution network of a microprocessor includes some type of power source that supplies power to a distribution system. The distribution system includes resistive, capacitive and inductive elements that are connected together in a complex electrical network. With the increased clock frequency of modem and high-performance microprocessors, limiting power dissipation has become a most stringent design target. Thus, it is mandatory for processor engineers to optimize a model depending on the power requirements in processor design.
FIG. 2 shows a prior art full-chip power modeling simulation in a microprocessor. CPU activity data is generated each cycle (20) and combined with power values per unit of the activity (22) using power model equations (24). Three values are provided for each type of activity data, corresponding to minimum (MIN), typical (TYP), and maximum (MAX) circuit power conditions. The CPU activity data changes every cycle. CPU activity data can include things such as (1) the number of instructions retired in the current cycle, (2) the number of 1's in a cache line being filled from memory, and/or (3) the number of instructions in stage 3 of the floating point multiplier.
The simulator calculates the power model equation results every cycle and sums them up for all equations/sub-blocks to generate full-chip MIN, TYP, and MAX (26). After the run, power data is analyzed/summarized by various methods including taking the average over all cycles and the peak variation in power from one cycle to the next. Average power can be used to estimate the sustained temperature that the cooling system must be designed to tolerate. Peak power variation can be used to design decoupling capacitors and other circuitry to tolerate changes in inductance.
FIG. 3 shows an example of simulation results generated from a prior art full-chip power modeling simulation. In this example, the simulation results include three types of power dissipation value, maximum (Max) (30), typical (Typ) (32), and minimum (Min) (34). These values are recorded and may change over time. The power behavior may be categorized in terms of characteristic factors. A “Peak” factor is defined as the highest power point reached in a run. A “Low” factor is defined as the lowest power point reached in a run. An “average” (Avg) factor is defined as an average over a run. Simulation results may be analyzed in terms of various methods. For example, they may be analyzed in terms of Peak, Avg, Low power values, or any other user-defined characteristic factors.
Power modeling in a cycle accurate simulator provides benefits including: the ability to run orders of magnitude in more cycles than is possible in RTL or circuit level simulators; the ability to generate meaningful results early enough in the design process to modify the design, e.g., targeting particular sub-blocks for power reduction and then managing inductance changes; understanding how power behavior correlates with performance factors such as instructions executed, cache miss rates, and other CPU activity information; providing another method of generating power data to confirm estimates by other means including trend projection and static summation of MIN, TYP, and MAX sub-block power; and the ability to develop and test power diagnostic programs to test corner cases such as sustaining high or low power before silicon is available.
Power simulation using MIN and MAX conditions provides bounds on the amount of variation that could exist that may not be apparent when simulating using only the TYP conditions. Optimizing the power modeling methodology for specific requirements such as described is needed due to the continuing increase in complexity of microprocessor design.